{
 "image": "mpw-001_HVTPM_reticle.png",
 "width": 53432,
 "height": 65056,
 "bit_depth": 8,
 "color_type": 0,
 "grid": {
  "rows": 6,
  "cols": 7,
  "die_w": 7176,
  "die_h": 10376,
  "gap": 400
 },
 "filter": {
  "rows": "up",
  "first_row_of_each_tile": "none"
 },
 "zlib": {
  "level": 9,
  "wbits": 15,
  "memlevel": 9,
  "strategy": 0,
  "idat_chunk_limit": 1048576
 },
 "rebuild_with": "reconstruct_reticle.py",
 "tiles": [
  {
   "file": "mpw-001_HVTPM_tile_A1.png",
   "row": 0,
   "col": 0,
   "frame": "A1",
   "x": 0,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "001",
   "project": "Caravel_Plus",
   "bytes": 203102,
   "sha256": "d074865cee3eb83d4c339cff2b88775cb7f3aa168efb28553a672fc12ae3acf7"
  },
  {
   "file": "mpw-001_HVTPM_tile_A2.png",
   "row": 0,
   "col": 1,
   "frame": "A2",
   "x": 7576,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "002",
   "project": "caravel_vdp_lite",
   "bytes": 148954,
   "sha256": "77c9d4a2719d5e489ff57091c4fc1c50f1f0429dccb374749bce623c7966eda5"
  },
  {
   "file": "mpw-001_HVTPM_tile_A3.png",
   "row": 0,
   "col": 2,
   "frame": "A3",
   "x": 15152,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "003",
   "project": "caravel-softshell",
   "bytes": 154979,
   "sha256": "0e6f809687e79234c64f7cf827529030a0d6d640f1b3744749883dfe407e5c51"
  },
  {
   "file": "mpw-001_HVTPM_tile_A4.png",
   "row": 0,
   "col": 3,
   "frame": "A4",
   "x": 22728,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "004",
   "project": "caravel_UNCC_MPW_1",
   "bytes": 174189,
   "sha256": "dfc6d8e5e251dc9c6bdbe3c5f2123641839d48778e89ce6b1178c2dbcd06708a"
  },
  {
   "file": "mpw-001_HVTPM_tile_A5.png",
   "row": 0,
   "col": 4,
   "frame": "A5",
   "x": 30304,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "005",
   "project": "caravel_sha3_256_crypto_",
   "bytes": 157625,
   "sha256": "898d794703217d12b38d0c878913609a82f45eb6a49567f9c17ef9c99aebeff9"
  },
  {
   "file": "mpw-001_HVTPM_tile_A6.png",
   "row": 0,
   "col": 5,
   "frame": "A6",
   "x": 37880,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "006",
   "project": "caravel_spectrometer",
   "bytes": 158457,
   "sha256": "ce3ae16cf3b91f86fba049227b777f98d05c83260f8621a6b3ca0070ea02a25c"
  },
  {
   "file": "mpw-001_HVTPM_tile_A7.png",
   "row": 0,
   "col": 6,
   "frame": "A7",
   "x": 45456,
   "y": 0,
   "w": 7976,
   "h": 10776,
   "slot": null,
   "project": null,
   "bytes": 106769,
   "sha256": "56c5b78f9b86a53fdb64304acc12fba53d045b0526cc20ac1552594029f8a19a"
  },
  {
   "file": "mpw-001_HVTPM_tile_B1.png",
   "row": 1,
   "col": 0,
   "frame": "B1",
   "x": 0,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "007",
   "project": "caravel_ibtida_soc",
   "bytes": 159299,
   "sha256": "e8ff6addee5bf555f2d8dda8200f7b191dc6c6a2604be1078d93f868327102b5"
  },
  {
   "file": "mpw-001_HVTPM_tile_B2.png",
   "row": 1,
   "col": 1,
   "frame": "B2",
   "x": 7576,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "008",
   "project": "caravel-hs32core",
   "bytes": 154414,
   "sha256": "c73bd1ae93b1f67b9d8f9764a726e5944cf1a8be58062d9dd77123c566d23598"
  },
  {
   "file": "mpw-001_HVTPM_tile_B3.png",
   "row": 1,
   "col": 2,
   "frame": "B3",
   "x": 15152,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "009",
   "project": "caravel_astria_testchip",
   "bytes": 149118,
   "sha256": "858b98002ebfcdaf9481743ffb07e8ee6e9e8836997960b022e95d7781717a15"
  },
  {
   "file": "mpw-001_HVTPM_tile_B4.png",
   "row": 1,
   "col": 3,
   "frame": "B4",
   "x": 22728,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "010",
   "project": "caravel_pyfive",
   "bytes": 152794,
   "sha256": "429156e23e947da97194c46f666d7b76924d0a01c018d1f34386ec30a88201c6"
  },
  {
   "file": "mpw-001_HVTPM_tile_B5.png",
   "row": 1,
   "col": 4,
   "frame": "B5",
   "x": 30304,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "011",
   "project": "caravel_fasoc",
   "bytes": 210033,
   "sha256": "1904497f45344192a62eb545b749f76c61b4589593b5dc4dab76c60acfa23661"
  },
  {
   "file": "mpw-001_HVTPM_tile_B6.png",
   "row": 1,
   "col": 5,
   "frame": "B6",
   "x": 37880,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "012",
   "project": "caravel-mph",
   "bytes": 153701,
   "sha256": "82e26be1e0175fc655c25b7d99178bb88d09dcb067b243de6c306123229197b0"
  },
  {
   "file": "mpw-001_HVTPM_tile_B7.png",
   "row": 1,
   "col": 6,
   "frame": "B7",
   "x": 45456,
   "y": 10776,
   "w": 7976,
   "h": 10776,
   "slot": "013",
   "project": "caravel_rapcores",
   "bytes": 150402,
   "sha256": "262b88928de46868fbb6be6cf5729933552bab7a7937178ad1a7587214b977dd"
  },
  {
   "file": "mpw-001_HVTPM_tile_C1.png",
   "row": 2,
   "col": 0,
   "frame": "C1",
   "x": 0,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "014",
   "project": "MorphleLogic",
   "bytes": 173955,
   "sha256": "cc2ba7fbb3c8907eca078bca3593131abec6c932f4463f0d5585c2b9a11bfaf7"
  },
  {
   "file": "mpw-001_HVTPM_tile_C2.png",
   "row": 2,
   "col": 1,
   "frame": "C2",
   "x": 7576,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "015",
   "project": "caravel_RT-PseudoRNG",
   "bytes": 147293,
   "sha256": "25b461b477ef0632e7ff54044c8d0a79c7cd4fe2c8fba3c2bb50d28cce795952"
  },
  {
   "file": "mpw-001_HVTPM_tile_C3.png",
   "row": 2,
   "col": 2,
   "frame": "C3",
   "x": 15152,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "016",
   "project": "caravel_amsat_txrx_ic",
   "bytes": 151553,
   "sha256": "5d002d1b8eab009fe55a11c9d74e3efaae20ef91898e2c4ba5fdb45af18afba0"
  },
  {
   "file": "mpw-001_HVTPM_tile_C4.png",
   "row": 2,
   "col": 3,
   "frame": "C4",
   "x": 22728,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "017",
   "project": "Caravel-SOFA-HD",
   "bytes": 157611,
   "sha256": "04f6fac0afb099db56716368940f52e567622b70e894a81ed02de9d3b05bf070"
  },
  {
   "file": "mpw-001_HVTPM_tile_C5.png",
   "row": 2,
   "col": 4,
   "frame": "C5",
   "x": 30304,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": null,
   "project": null,
   "bytes": 102728,
   "sha256": "404d2b68827b8f64404c8d26b19179b934888b57260a33a16e25162769e85650"
  },
  {
   "file": "mpw-001_HVTPM_tile_C6.png",
   "row": 2,
   "col": 5,
   "frame": "C6",
   "x": 37880,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "018",
   "project": "caravel_Ghazi_SoC",
   "bytes": 163225,
   "sha256": "a49afa5445d83d56b233e843ae9b831759518fac9e62aa37d04190688719ab7a"
  },
  {
   "file": "mpw-001_HVTPM_tile_C7.png",
   "row": 2,
   "col": 6,
   "frame": "C7",
   "x": 45456,
   "y": 21552,
   "w": 7976,
   "h": 10776,
   "slot": "019",
   "project": "caravel_fulgor_opamp",
   "bytes": 149185,
   "sha256": "59af113a21e9dd0f77ecd05c60199b0d3baf617c6b8e028493a19f64d9b11fb6"
  },
  {
   "file": "mpw-001_HVTPM_tile_D1.png",
   "row": 3,
   "col": 0,
   "frame": "D1",
   "x": 0,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "020",
   "project": "q-rib",
   "bytes": 144833,
   "sha256": "7f1c355513d7bbb0d02ba7419fa171fe12b475c1409bfc0c64b83b833b1905f9"
  },
  {
   "file": "mpw-001_HVTPM_tile_D2.png",
   "row": 3,
   "col": 1,
   "frame": "D2",
   "x": 7576,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "021",
   "project": "caravel_fwpayload",
   "bytes": 148969,
   "sha256": "430d0779ddf1cba3e9007b142aafe9d2fb9d467ac991df4c18e1f1d7eea94f5d"
  },
  {
   "file": "mpw-001_HVTPM_tile_D3.png",
   "row": 3,
   "col": 2,
   "frame": "D3",
   "x": 15152,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "022",
   "project": "caravel_OpenTDC",
   "bytes": 181345,
   "sha256": "4f453e423a5083d86311bc395b092f58ba1fad040ce45994871235ad84b5b883"
  },
  {
   "file": "mpw-001_HVTPM_tile_D4.png",
   "row": 3,
   "col": 3,
   "frame": "D4",
   "x": 22728,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "023",
   "project": "caravel_analog_rf",
   "bytes": 114602,
   "sha256": "0808ba75bee4161462b0c8134b25ffe2bad8ec66a4918dcd557f2be3c3e2b35a"
  },
  {
   "file": "mpw-001_HVTPM_tile_D5.png",
   "row": 3,
   "col": 4,
   "frame": "D5",
   "x": 30304,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "024",
   "project": "Caravel_Fault_SPM",
   "bytes": 146435,
   "sha256": "60cccb783c10b0c3b01f21533d2af9406aec48030e6f6cf00abe8e766a6d35db"
  },
  {
   "file": "mpw-001_HVTPM_tile_D6.png",
   "row": 3,
   "col": 5,
   "frame": "D6",
   "x": 37880,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "025",
   "project": "caravel_skywater130_decr",
   "bytes": 159663,
   "sha256": "9c20c2df368c3965d332746c45aae6b7f8d6858f284a54b1376bf02de16b2ca9"
  },
  {
   "file": "mpw-001_HVTPM_tile_D7.png",
   "row": 3,
   "col": 6,
   "frame": "D7",
   "x": 45456,
   "y": 32328,
   "w": 7976,
   "h": 10776,
   "slot": "026",
   "project": "microwatt-caravel",
   "bytes": 185514,
   "sha256": "6108dd7f3ab530d30393ee9fa45ff6e64ab0fa35becb98e881f275074bfc5539"
  },
  {
   "file": "mpw-001_HVTPM_tile_E1.png",
   "row": 4,
   "col": 0,
   "frame": "E1",
   "x": 0,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "027",
   "project": "caravel_mram",
   "bytes": 144853,
   "sha256": "a963822c3b78cb271ba6039c5b54ae9f099db801b6d8dc58b533dc76ff73050a"
  },
  {
   "file": "mpw-001_HVTPM_tile_E2.png",
   "row": 4,
   "col": 1,
   "frame": "E2",
   "x": 7576,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "028",
   "project": "Caravel_EL2_SoC",
   "bytes": 211567,
   "sha256": "3ca3336253ffc82a0a4503478a4fc3eaba98141f870dc230d1f6b70dea4dee3f"
  },
  {
   "file": "mpw-001_HVTPM_tile_E3.png",
   "row": 4,
   "col": 2,
   "frame": "E3",
   "x": 15152,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "029",
   "project": "caravel_aes",
   "bytes": 154256,
   "sha256": "e138702674cc37e4cc937cf725fff75f68f2a23e7ed57b47239cd688b0f7f915"
  },
  {
   "file": "mpw-001_HVTPM_tile_E4.png",
   "row": 4,
   "col": 3,
   "frame": "E4",
   "x": 22728,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "030",
   "project": "Caravel-OpenFPGA-EF",
   "bytes": 213838,
   "sha256": "43fa3e65802671bf660b4a3c4f1a869fdd820ebf31da34037cde260e3d7692c6"
  },
  {
   "file": "mpw-001_HVTPM_tile_E5.png",
   "row": 4,
   "col": 4,
   "frame": "E5",
   "x": 30304,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "031",
   "project": "Caravel_Chameleon_SoC",
   "bytes": 233117,
   "sha256": "b38e04ee371ef5198d97c356713d7a18263cc6167b337ce2ac3b11a8706d4a54"
  },
  {
   "file": "mpw-001_HVTPM_tile_E6.png",
   "row": 4,
   "col": 5,
   "frame": "E6",
   "x": 37880,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "032",
   "project": "Caravel_N5_SoC",
   "bytes": 232691,
   "sha256": "aad2f985ec52e051a0c53e98791d19a6e9c590c59fa4d5533dfc307edb18053e"
  },
  {
   "file": "mpw-001_HVTPM_tile_E7.png",
   "row": 4,
   "col": 6,
   "frame": "E7",
   "x": 45456,
   "y": 43104,
   "w": 7976,
   "h": 10776,
   "slot": "033",
   "project": "caravel_linsorter",
   "bytes": 161909,
   "sha256": "b9a3607ae149912797220d09170c5df61b1aff847d75b3cd9ed85b1038d3facc"
  },
  {
   "file": "mpw-001_HVTPM_tile_F1.png",
   "row": 5,
   "col": 0,
   "frame": "F1",
   "x": 0,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "034",
   "project": "caravel_fpga250",
   "bytes": 233982,
   "sha256": "baa1015322eb2974437f788098749f33368ccc9e68e10c05b200454716156984"
  },
  {
   "file": "mpw-001_HVTPM_tile_F2.png",
   "row": 5,
   "col": 1,
   "frame": "F2",
   "x": 7576,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "035",
   "project": "crypto-accelerator-build",
   "bytes": 154673,
   "sha256": "4f0fda72b8feeeccae2244dd7e2f21987fe87c8fc260f97c7719c3248ec4a9dd"
  },
  {
   "file": "mpw-001_HVTPM_tile_F3.png",
   "row": 5,
   "col": 2,
   "frame": "F3",
   "x": 15152,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "036",
   "project": "Caravel-QLSOFA-HD",
   "bytes": 170692,
   "sha256": "bc19c7c091b11e6074bb0f0e3b93ba345e2bd15e695ea224a1c1784ae7efeaf2"
  },
  {
   "file": "mpw-001_HVTPM_tile_F4.png",
   "row": 5,
   "col": 3,
   "frame": "F4",
   "x": 22728,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "037",
   "project": "G_Skywater130nm_1stTO",
   "bytes": 150010,
   "sha256": "020c1b7b54e9996d67dbc90a056a3792bbcbf46b095e75d39928623047cf364b"
  },
  {
   "file": "mpw-001_HVTPM_tile_F5.png",
   "row": 5,
   "col": 4,
   "frame": "F5",
   "x": 30304,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "038",
   "project": "caravel_DSP48_DAC",
   "bytes": 150860,
   "sha256": "2a12510938a463335f94f2e8863d9387cff9118a8957243ad785555549d8403a"
  },
  {
   "file": "mpw-001_HVTPM_tile_F6.png",
   "row": 5,
   "col": 5,
   "frame": "F6",
   "x": 37880,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "039",
   "project": "Caravel-SOFA-CHD",
   "bytes": 172374,
   "sha256": "0c99ef27ac9542046e092b642539451380c8513d435c26ca81a7be35ffc3420e"
  },
  {
   "file": "mpw-001_HVTPM_tile_F7.png",
   "row": 5,
   "col": 6,
   "frame": "F7",
   "x": 45456,
   "y": 53880,
   "w": 7976,
   "h": 11176,
   "slot": "040",
   "project": "caravel_riscv_osu",
   "bytes": 165923,
   "sha256": "e30d1f8ae39195c5f95260a1af5825eb95f8587decb15a203ce23130776e9412"
  }
 ],
 "sha256": {
  "png": "b0643b489f4d931999dca1f76faaee3b73e4b9b7b9f0d032283701b8d2b03a78",
  "filtered_stream": "633a0efd5c316dee7b007397f9e470dbae72afe760b484346a4798d6e609b4e3",
  "pixels": "584469bd0574895b79691d8b58d2414e2024a6c2e8cbec7af218cad78bece6ad"
 }
}