{
 "image": "mpw-001_URPM_reticle.png",
 "width": 53432,
 "height": 65056,
 "bit_depth": 8,
 "color_type": 0,
 "grid": {
  "rows": 6,
  "cols": 7,
  "die_w": 7176,
  "die_h": 10376,
  "gap": 400
 },
 "filter": {
  "rows": "up",
  "first_row_of_each_tile": "none"
 },
 "zlib": {
  "level": 9,
  "wbits": 15,
  "memlevel": 9,
  "strategy": 0,
  "idat_chunk_limit": 1048576
 },
 "rebuild_with": "reconstruct_reticle.py",
 "tiles": [
  {
   "file": "mpw-001_URPM_tile_A1.png",
   "row": 0,
   "col": 0,
   "frame": "A1",
   "x": 0,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "001",
   "project": "Caravel_Plus",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_A2.png",
   "row": 0,
   "col": 1,
   "frame": "A2",
   "x": 7576,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "002",
   "project": "caravel_vdp_lite",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_A3.png",
   "row": 0,
   "col": 2,
   "frame": "A3",
   "x": 15152,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "003",
   "project": "caravel-softshell",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_A4.png",
   "row": 0,
   "col": 3,
   "frame": "A4",
   "x": 22728,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "004",
   "project": "caravel_UNCC_MPW_1",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_A5.png",
   "row": 0,
   "col": 4,
   "frame": "A5",
   "x": 30304,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "005",
   "project": "caravel_sha3_256_crypto_",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_A6.png",
   "row": 0,
   "col": 5,
   "frame": "A6",
   "x": 37880,
   "y": 0,
   "w": 7576,
   "h": 10776,
   "slot": "006",
   "project": "caravel_spectrometer",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_A7.png",
   "row": 0,
   "col": 6,
   "frame": "A7",
   "x": 45456,
   "y": 0,
   "w": 7976,
   "h": 10776,
   "slot": null,
   "project": null,
   "bytes": 106769,
   "sha256": "56c5b78f9b86a53fdb64304acc12fba53d045b0526cc20ac1552594029f8a19a"
  },
  {
   "file": "mpw-001_URPM_tile_B1.png",
   "row": 1,
   "col": 0,
   "frame": "B1",
   "x": 0,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "007",
   "project": "caravel_ibtida_soc",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_B2.png",
   "row": 1,
   "col": 1,
   "frame": "B2",
   "x": 7576,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "008",
   "project": "caravel-hs32core",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_B3.png",
   "row": 1,
   "col": 2,
   "frame": "B3",
   "x": 15152,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "009",
   "project": "caravel_astria_testchip",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_B4.png",
   "row": 1,
   "col": 3,
   "frame": "B4",
   "x": 22728,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "010",
   "project": "caravel_pyfive",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_B5.png",
   "row": 1,
   "col": 4,
   "frame": "B5",
   "x": 30304,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "011",
   "project": "caravel_fasoc",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_B6.png",
   "row": 1,
   "col": 5,
   "frame": "B6",
   "x": 37880,
   "y": 10776,
   "w": 7576,
   "h": 10776,
   "slot": "012",
   "project": "caravel-mph",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_B7.png",
   "row": 1,
   "col": 6,
   "frame": "B7",
   "x": 45456,
   "y": 10776,
   "w": 7976,
   "h": 10776,
   "slot": "013",
   "project": "caravel_rapcores",
   "bytes": 106943,
   "sha256": "1ea2e623c99a7e647cbad34bb1ab1a8d6e67cfe2845dcef8ca0bb78253189654"
  },
  {
   "file": "mpw-001_URPM_tile_C1.png",
   "row": 2,
   "col": 0,
   "frame": "C1",
   "x": 0,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "014",
   "project": "MorphleLogic",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_C2.png",
   "row": 2,
   "col": 1,
   "frame": "C2",
   "x": 7576,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "015",
   "project": "caravel_RT-PseudoRNG",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_C3.png",
   "row": 2,
   "col": 2,
   "frame": "C3",
   "x": 15152,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "016",
   "project": "caravel_amsat_txrx_ic",
   "bytes": 103731,
   "sha256": "2773d8e591fc52f199f73f5d21048e3b3d69e0ef13bec385eac08ec571c5d46f"
  },
  {
   "file": "mpw-001_URPM_tile_C4.png",
   "row": 2,
   "col": 3,
   "frame": "C4",
   "x": 22728,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "017",
   "project": "Caravel-SOFA-HD",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_C5.png",
   "row": 2,
   "col": 4,
   "frame": "C5",
   "x": 30304,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": null,
   "project": null,
   "bytes": 102728,
   "sha256": "404d2b68827b8f64404c8d26b19179b934888b57260a33a16e25162769e85650"
  },
  {
   "file": "mpw-001_URPM_tile_C6.png",
   "row": 2,
   "col": 5,
   "frame": "C6",
   "x": 37880,
   "y": 21552,
   "w": 7576,
   "h": 10776,
   "slot": "018",
   "project": "caravel_Ghazi_SoC",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_C7.png",
   "row": 2,
   "col": 6,
   "frame": "C7",
   "x": 45456,
   "y": 21552,
   "w": 7976,
   "h": 10776,
   "slot": "019",
   "project": "caravel_fulgor_opamp",
   "bytes": 106943,
   "sha256": "1ea2e623c99a7e647cbad34bb1ab1a8d6e67cfe2845dcef8ca0bb78253189654"
  },
  {
   "file": "mpw-001_URPM_tile_D1.png",
   "row": 3,
   "col": 0,
   "frame": "D1",
   "x": 0,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "020",
   "project": "q-rib",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_D2.png",
   "row": 3,
   "col": 1,
   "frame": "D2",
   "x": 7576,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "021",
   "project": "caravel_fwpayload",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_D3.png",
   "row": 3,
   "col": 2,
   "frame": "D3",
   "x": 15152,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "022",
   "project": "caravel_OpenTDC",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_D4.png",
   "row": 3,
   "col": 3,
   "frame": "D4",
   "x": 22728,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "023",
   "project": "caravel_analog_rf",
   "bytes": 103057,
   "sha256": "251c0fd06fe0b3d4835ffecff86135295f5ca8bc4088230c83cfdefeaf1dcd52"
  },
  {
   "file": "mpw-001_URPM_tile_D5.png",
   "row": 3,
   "col": 4,
   "frame": "D5",
   "x": 30304,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "024",
   "project": "Caravel_Fault_SPM",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_D6.png",
   "row": 3,
   "col": 5,
   "frame": "D6",
   "x": 37880,
   "y": 32328,
   "w": 7576,
   "h": 10776,
   "slot": "025",
   "project": "caravel_skywater130_decr",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_D7.png",
   "row": 3,
   "col": 6,
   "frame": "D7",
   "x": 45456,
   "y": 32328,
   "w": 7976,
   "h": 10776,
   "slot": "026",
   "project": "microwatt-caravel",
   "bytes": 106943,
   "sha256": "1ea2e623c99a7e647cbad34bb1ab1a8d6e67cfe2845dcef8ca0bb78253189654"
  },
  {
   "file": "mpw-001_URPM_tile_E1.png",
   "row": 4,
   "col": 0,
   "frame": "E1",
   "x": 0,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "027",
   "project": "caravel_mram",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_E2.png",
   "row": 4,
   "col": 1,
   "frame": "E2",
   "x": 7576,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "028",
   "project": "Caravel_EL2_SoC",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_E3.png",
   "row": 4,
   "col": 2,
   "frame": "E3",
   "x": 15152,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "029",
   "project": "caravel_aes",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_E4.png",
   "row": 4,
   "col": 3,
   "frame": "E4",
   "x": 22728,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "030",
   "project": "Caravel-OpenFPGA-EF",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_E5.png",
   "row": 4,
   "col": 4,
   "frame": "E5",
   "x": 30304,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "031",
   "project": "Caravel_Chameleon_SoC",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_E6.png",
   "row": 4,
   "col": 5,
   "frame": "E6",
   "x": 37880,
   "y": 43104,
   "w": 7576,
   "h": 10776,
   "slot": "032",
   "project": "Caravel_N5_SoC",
   "bytes": 102906,
   "sha256": "c74c6326866625628dccd48f509efdfe533ec7c9a093c77f34e8efa5a1ffd320"
  },
  {
   "file": "mpw-001_URPM_tile_E7.png",
   "row": 4,
   "col": 6,
   "frame": "E7",
   "x": 45456,
   "y": 43104,
   "w": 7976,
   "h": 10776,
   "slot": "033",
   "project": "caravel_linsorter",
   "bytes": 106943,
   "sha256": "1ea2e623c99a7e647cbad34bb1ab1a8d6e67cfe2845dcef8ca0bb78253189654"
  },
  {
   "file": "mpw-001_URPM_tile_F1.png",
   "row": 5,
   "col": 0,
   "frame": "F1",
   "x": 0,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "034",
   "project": "caravel_fpga250",
   "bytes": 106722,
   "sha256": "9ded6d42a8df876f7737103f55abf7e4e49aeadcbeb7b813728139d01fb3eb3e"
  },
  {
   "file": "mpw-001_URPM_tile_F2.png",
   "row": 5,
   "col": 1,
   "frame": "F2",
   "x": 7576,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "035",
   "project": "crypto-accelerator-build",
   "bytes": 106722,
   "sha256": "9ded6d42a8df876f7737103f55abf7e4e49aeadcbeb7b813728139d01fb3eb3e"
  },
  {
   "file": "mpw-001_URPM_tile_F3.png",
   "row": 5,
   "col": 2,
   "frame": "F3",
   "x": 15152,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "036",
   "project": "Caravel-QLSOFA-HD",
   "bytes": 106722,
   "sha256": "9ded6d42a8df876f7737103f55abf7e4e49aeadcbeb7b813728139d01fb3eb3e"
  },
  {
   "file": "mpw-001_URPM_tile_F4.png",
   "row": 5,
   "col": 3,
   "frame": "F4",
   "x": 22728,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "037",
   "project": "G_Skywater130nm_1stTO",
   "bytes": 107294,
   "sha256": "670d11add3aaebb52cb86b443b25507de69e38a791e675ae9ec22284e3bf1b15"
  },
  {
   "file": "mpw-001_URPM_tile_F5.png",
   "row": 5,
   "col": 4,
   "frame": "F5",
   "x": 30304,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "038",
   "project": "caravel_DSP48_DAC",
   "bytes": 106722,
   "sha256": "9ded6d42a8df876f7737103f55abf7e4e49aeadcbeb7b813728139d01fb3eb3e"
  },
  {
   "file": "mpw-001_URPM_tile_F6.png",
   "row": 5,
   "col": 5,
   "frame": "F6",
   "x": 37880,
   "y": 53880,
   "w": 7576,
   "h": 11176,
   "slot": "039",
   "project": "Caravel-SOFA-CHD",
   "bytes": 106722,
   "sha256": "9ded6d42a8df876f7737103f55abf7e4e49aeadcbeb7b813728139d01fb3eb3e"
  },
  {
   "file": "mpw-001_URPM_tile_F7.png",
   "row": 5,
   "col": 6,
   "frame": "F7",
   "x": 45456,
   "y": 53880,
   "w": 7976,
   "h": 11176,
   "slot": "040",
   "project": "caravel_riscv_osu",
   "bytes": 110893,
   "sha256": "9e06b4872fc5c8c585fb56165102a9e9b139f22296c966e977b3442f5377cc6c"
  }
 ],
 "sha256": {
  "png": "71fa2e625372931bab19149000e1a91900995a0f836082dfd400ffce13633af9",
  "filtered_stream": "ab367ecdae38982f1d1a3350991f8911117933cd591b02737df76a714458168f",
  "pixels": "26830cc7cb60b4017a8eb9c0f578591ad5a252980d98184ef323d1c1417a5aa0"
 }
}